1. Field of the Invention
The present invention relates to a DLL (Delay Lock Loop) circuit used in a DDR SDRAM, and more particularly to a DLL circuit that is operable even if the frequency of an external clock inputted to the DLL circuit is high.
2. Description of the Prior Art
As generally known in the art, in the DDR SDRAM, a DLL circuit, which is an internal clock generating circuit, is used in order to synchronize an output time of data with an externally inputted clock (e.g., external clock). That is, since a time delay occurs due to internal circuits in the case that the externally inputted clock is used as an internal clock, the DLL circuit is used to make the internal clock and the external clock have the same phase in order to compensate for the time delay. In other words, the DLL circuit is used to cause data to be outputted in synchronization with the external clock.
FIG. 1 is a block diagram of a general DLL circuit.
As illustrated in FIG. 1, the DLL circuit includes a clock buffer 10 for receiving an external clock signal, a delay circuit 20 for receiving an output signal of the clock buffer 10, a clock divider 50 for dividing the output signal of the clock buffer 10, a dummy delay circuit 60 for delaying an output signal of the clock divider 50 for a predetermined time, a replica delay unit 90 for delaying an output signal of the dummy delay circuit 60, a phase comparator 70 for comparing a phase of an output signal of the replica delay unit 90 with a phase of the output signal of the clock divider 50, a delay controller 80 for receiving an output signal of the phase comparator 70 and controlling delay operations of the delay circuit 20 and the dummy delay circuit 60, and a clock signal line 30 for receiving an output signal of the delay circuit 20 and controlling a data output of an output buffer 40.
The clock buffer 10 is a buffer circuit that converts the potential level of the externally inputted clock signal into a potential level used in the DDR SDRAM.
The delay circuit 20 is a delay line that receives the output signal (which is used as the internal clock) of the clock buffer 10, and changes the delay time of the received clock signal. An example of the delay circuit 20 is illustrated in FIG. 2, and as illustrated, it includes a plurality of unit delay circuits.
The clock signal line 30 is a clock driving device that receives the output signal of the delay circuit 20, and generates a driving signal for driving the data output buffer 40.
The output buffer 40 outputs the data transferred from a data bus to an external output terminal in response to the driving signal from the clock signal line 30.
The clock divider 50 divides the frequency of the clock signal outputted from the clock buffer 10 into 1/n, and generates a specified reference clock (generally, n is an integer, i.e., 4, 8 or 16). That is, the clock divider 50 divides the frequency of the internal clock into ½M (here, M is the number of unit dividers provided in the clock divider).
The dummy delay circuit 60 is a delay line that receives the reference clock outputted from the clock divider, and changes the delay time of the reference clock. It is general that the dummy delay circuit 60 has the same structure as the delay circuit 20.
The replica delay unit 90 is a delay unit that has a time delay existing from the input of the clock signal to the DLL circuit to the output of the data through the data output buffer.
The phase comparator 70 compares the phase of the output signal of the clock divider 50 with the phase of the output signal of the replica delay unit 90, and controls the delay controller 80. That is, the phase comparator 70 compares the difference of time delay of the two received signals, and generates a signal for controlling the delay controller 80 that is composed of registers. For reference, FIGS. 4 and 6 illustrate the delay controller 80 and the phase comparator 70, respectively, and as illustrated, the delay controller 80 is controlled by output signals left1, left2, right1 and right2 of the phase comparator 70.
The delay controller 80 illustrated in FIG. 4 is composed of registers for controlling a unit delay in respective delay lines which constitute the delay circuit 20 and the dummy delay circuit 60. The delay controller 80 adjusts the delay time of the delay circuit 20 and the dummy delay circuit 60, and respective register values are controlled by the output signals of the phase comparator 70.
Hereinafter, the construction of a conventional DLL circuit will be explained in more detail.
FIG. 2 illustrates an example of a general delay circuit 20 illustrated in FIG. 1. As shown in FIG. 2, the delay circuit 20 includes a plurality of unit delays which are controlled by the delay controller. The output signal of the clock buffer 10 is applied to the respective unit delays. The respective unit delay includes a first NAND gate for receiving the output signal of the clock buffer 10 and the output signal of the delay controller 80, a second NAND gate for receiving an output signal of the preceding unit delay and an output signal of the first NAND gate, and an inverter for inverting an output signal of the second NAND gate. To input terminals of the second NAND gate of the first unit delay, an output signal of the first NAND gate and a power supply voltage Vdd are inputted.
In operation, it is assumed that to the input terminals of the first NAND gate of the second unit delay, the output signal of the clock buffer 10 and a register signal of the delay controller are inputted.
If the register signal is high in logic, the unit delay is enabled, and transfers the clock signal (i.e., CLK of FIG. 2) that is the output signal of the clock buffer 10.
If the register signal is low in logic, the output signal of the unit delay becomes high in logic, and is applied to the second NAND gate. Thus, a unit delay signal of the first unit delay is transferred to the following unit delay through the second NAND gate. In this case, a predetermined time delay occurs in the second NAND gate, and the inverter of the unit delay causes the same time delay as the second NAND gate. For reference, the dummy delay circuit 60 has the same construction as the delay circuit 20 as described above.
FIG. 3 illustrates the delay circuit 20 and the dummy delay circuit 60, which have a plurality of unit delays. In FIG. 3, a unit delay block UD denotes the unit delay of FIG. 2. The respective unit delays in the delay circuit 20 and the dummy delay circuit 60 are controlled through the delay controller 80 as described above.
FIG. 4 illustrates an example of a delay control circuit. Diverse modifications of such a delay control circuit, all having the same function, can be implemented by those skilled in the art.
FIG. 5 illustrates an example of the clock buffer 10 and the clock divider 50. The clock buffer 10 is a differential comparator circuit that receives externally inputted clock signals eclk and /eclk, and generates an internal clock signal. Generally, the clock buffer 10 is composed of a first clock buffer and a second clock buffer. The first clock buffer receives the external clock, and outputs the internal clock that is generated in synchronization with a rising edge of the external clock. The second clock buffer receives the external clock, and outputs the internal clock that is generated in synchronization with a falling edge of the external clock. The construction and operation of the clock buffer 10 are well known in the art, and a further explanation thereof will be omitted.
The clock divider 50 illustrated in FIG. 5 includes first to third dividers 51, 52 and 53, which are connected in series. That is, an output signal of the first divider 51 is applied to an input terminal of the second divider 52, and an output signal of the second divider 52 is applied to an input terminal of the third divider 53.
The first divider 51 receives the internal clock CLK, which is the output signal of the clock buffer 10, and outputs the clock signal Clk_1, which is obtained by dividing the frequency of the internal clock into ½. The second divider 52 outputs the clock signal Clk_2, which is obtained by dividing the frequency of the output signal Clk_1 of the first divider into ½. Accordingly, the frequency of the output signal of the second divider is ¼ of the frequency of the internal clock. The third divider 53 outputs the clock signal Clk_3, which is obtained by dividing the frequency of the output signal Clk_2 of the second divider 52 into ½. Accordingly, the frequency of the output signal of the third divider is ⅛ of the frequency of the internal clock. The construction, modification and operation of the clock divider 50 are well known in the art, and a further explanation thereof will be omitted.
FIG. 6 illustrates an example of the phase comparator 70 of FIG. 1. The phase comparator 70 compares the output signal Clk_3 of the clock divider 50 with an output signal Clk_delay of the replica delay unit 90, and reduces the time difference between two output signals. In other words, the phase comparator 70 controls a moving direction of registers in the delay controller by comparing the output signal Clk_3 of the clock divider 50 with the output signal Clk_delay of the replica delay unit 90. The phase comparator 70 continues the comparing work until the rising edge of the output signal of the clock divider 50 is synchronized with the rising edge of the output signal of the replica delay unit 90, and the phase difference between them becomes 0. The output signals left1, left2, right1 and right2 of the phase comparator 70 are used to control the delay controller 80 composed of registers.
FIG. 7 is a timing diagram explaining the operation of the phase comparator of FIG. 6.
Referring to FIGS. 6 and 7, the clock signal Clk_3 represents the output signal of the clock divider (of FIG. 5) that divided the internal clock into ⅛, and the clock signal ref represents an inverted signal of the clock signal Clk_3 as illustrated in FIG. 6. The clock signal Clk_delay is the output signal of the replica delay unit 90.
The left part of FIG. 7 shows a case in which the rising edge of the clock signal Clk_delay is faster than the rising edge of the clock signal ref. In this case, an added delay becomes in a high level, and this controls the controller in a direction in which the delay time increases. That is, the shift left signal left1 becomes a high level.
The right part of FIG. 7 shows a case in which the rising edge of the clock signal Clk_delay is later than the rising edge of the clock signal ref. In this case, a reduced delay becomes in a high level, and this controls the controller in a direction in which the delay time decreases. That is, the shift left signal left2 becomes a high level.
FIG. 8 is a timing diagram of the conventional delay circuit.
In FIG. 8, TCK denotes a period of the clock signal, and T1 denotes a delay time occurring as the externally inputted clock passes through the clock buffer.
T2 denotes a delay time occurring from the input of the external clock to the output of the data, and is the same as the delay time of the delay unit 90.
Td denotes a delay time which should be adjusted in the delay circuit 20 by the delay controller 80.
CLK_DLL denotes the output signal of the clock signal line 30 which controls the data output buffer 40, and dout denotes data which is outputted from the data output buffer 40.
CLK_3 and CLK_3b denote final output signals of the clock divider, and CLK_3 delay denotes the output signal of the replica delay unit.
Generally, the DLL circuit, in order to output the data in synchronization with the external input clock, applies the clock signal, which passed through the clock buffer, to the clock divider, and compares the phase of the output signal of the clock divider with the phase of the signal, which was outputted from the clock divider and passed through the specified delay means (i.e., dummy delay circuit and replica delay unit). Based on this, the phase comparator controls the delay controller to repeat the adjustment of the delay time Td occurring in the dummy delay circuit and the delay circuit.
However, as shown in FIG. 8, the conventional delay circuit causes no problem in a case in which the delay time T2 in the replica delay unit is shorter than the period TCK of the external input clock, but cannot perform a normal operation in the case in which the period of the external input clock is shorter than the delay time in the replica delay circuit.
In other words, in the case where the period TCK of the external input clock (e.g., pulse width of the external input clock) is longer than the delay time of the replica delay circuit, the conventional delay circuit can output the clock signal synchronized with the external signal by adjusting the delay time in the dummy delay circuit 60, but in the case where the period TCK of the external input clock is shorter than the delay time of the replica delay circuit, the clock signal delayed as long as the delay time in the replica delay circuit would be applied to the phase comparator even if the delay time in the dummy delay circuit is 0, and in this case, the conventional delay circuit cannot generate the clock signal synchronized with the external signal.